Results & Analysis

The main consideration when fitting together the different subsystems was timing. We had to keep in mind the ordering of the sampling, the sampling frequency, and the rate of which we input and output audio. Most notably, we had to ensure that timing did not disobey Nyquist’s theorem, which states “that an analog signal can be digitized without aliasing error if and only if the sampling rate is greater than or equal to twice the highest frequency component in a given signal.” Wearable Sensors (Second Edition), 2021

We anticipated two types of timing constraints: First, constraints on the sampling rate to ensure that we could support the full range of human hearing and second timing delays between when we input audio versus output audio. We decided that the latter would not impact the usability of our system, as the propagration delay would be too small to hear. As for the first, to capture the full human hearing range of roughly 20 Hz to 20,000 Hz, the sampling rate must be greater than 40 kHz, according to Nyquist’s.

The source clock for I2S communication between the PCM1808 and the FPGA was set to 24Mhz. From the PCM1808 datasheet, we know that the system clock (SCKI) runs at \(256*F_s\), and that there is an internal clock divider, such that the bit clock (BCK) runs at \(64*F_s\) and the left-right clock (LRCK) runs at \(F_s\). Therefore, we get that our sampling frequency, \(F_s\), is 93.75 kHz, making it so that we can sample frequencies up to 46.875 kHz. We also need to ensure that this sampling rate is preserved throughout so that we are outputting signals at the same rate we are reading them in.

The next stage for audio is to be passed to from the FPGA to the MCU for output, which we do with SPI. The SPI source clock (SCK) runs at $master clock / 2^{(BR+1)} $ . Therefore, \(SCK = 80MHz / 2^{1+1} = 80MHz*4 = 20MHz\). Each SPI transaction involves sending the 4 potentiometer values, then recieving an audio sample. This requires a handshake between the MCU and FPGA handeled by load and done flags to indicate when each system is ready to output and recieve. Nonetheless, from analysis of the logic analyzer, each SPI communication (including loading and receiving the data) ran faster than 93.75 kHz, making it so that out throughput can be preserved.

The final step for audio was for DMA to move audio data to the MCU DAC output register, where it read out on PA4 and PA5. This DMA transfer was triggered by TIM7, which was set to run as fast as possible. Recall that \(Timer freq = \frac{clkfreq}{PSC + 1} = \frac{80 MHz}{10} = 8MHz\). As we set ARR = 9, then we get that a reload event is triggered every 800kHz. Therefore, the output is faster than the sampling rate of 93.75 kHz. This is suitable for the system, because DMA is set to a circular buffer, meaning that it will continuously output copies of the audio amplitude until it is updated.

By designing the system in this way, we allowed ourselves to have flexibility for timing. The constraining factor on output resolution is the input sampling frequency set to 93.75 kHz. Therefore, our system can output frequencies up to 46.875 kHz, which satisfies the range of human hearing.